I2C Registers
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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.14 I2CSOAR Register (Offset = 800h) [reset = 0h]
I2CSOAR is shown in Figure 7-27 and described in Table 7-18.
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This register consists of seven address bits that identify the TM4E111BE6ZRB I2C device on the I2C bus.
Figure 7-27. I2CSOAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED OAR
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-18. I2CSOAR Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R 0h
6-0 OAR R/W 0h
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
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