Texas Instruments CC3235 SimpleLink Series - AES_KEY2_0 Register; AES_KEY2_1 Register; AES_KEY2_0 Register Field Descriptions; AES_KEY2_1 Register Field Descriptions

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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.7 AES_KEY2_0 Register (Offset = 18h) [reset = 0h]
AES_KEY2_0 is shown in Figure 17-20 and described in Table 17-10.
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XTS/CCM/CBC-MAC second key (LSW), hash key input (LSW).
Figure 17-20. AES_KEY2_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-10. AES_KEY2_0 Register Field Descriptions
Bit Field Type Reset Description
31-0 KEY R/W 0h
Key data
17.4.8 AES_KEY2_1 Register (Offset = 1Ch) [reset = 0h]
AES_KEY2_1 is shown in Figure 17-21 and described in Table 17-11.
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XTS/CCM/CBC-MAC second key (LSW), hash key input.
Figure 17-21. AES_KEY2_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-11. AES_KEY2_1 Register Field Descriptions
Bit Field Type Reset Description
31-0 KEY R/W 0h
Key data