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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.3 DMA_CTLBASE Register (offset = 8h) [reset = 0h]
DMA_CTLBASE is shown in Figure 4-9 and described in Table 4-13.
Contain the base address of control table. The base address must be aligned to 1024 byte boundary.
Figure 4-9. DMA_CTLBASE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR RESERVED
R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-13. DMA_CTLBASE Register Field Descriptions
Bit Field Type Reset Description
31-10 ADDR R/W 0h Channel Control Base Address.
This field contains the pointer to the base address of the channel
control table.
The base address must be
1024-byte aligned.
9-0 RESERVED R 0h
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