Texas Instruments CC3235 SimpleLink Series - GPT0 SWRST Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.31 GPT0SWRST Register (offset = 94h) [reset = 0h]
GPT0SWRST is shown in Figure 15-34 and described in Table 15-34.
Figure 15-34. GPT0SWRST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENSTS SWRST
R-0h R-0h R/W-0h
Table 15-34. GPT0SWRST Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENSTS R 0h
GPT_A0_ENABLED_STATUS
0h = GPT_A0 clocks and resets are disabled
1h = GPT_A0 clocks and resets are enabled
0 SWRST R/W 0h
GPT_A0_SOFT_RESET
0h = Deassert the soft reset for GPT_A0
1h = Assert the soft reset for GPT_A0