PRCM Registers
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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.8 SDIOMSWRST Register (offset = 28h) [reset = 0h]
SDIOMSWRST is shown in Figure 15-11 and described in Table 15-11.
Figure 15-11. SDIOMSWRST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENSTS SWRST
R-0h R-0h R/W-0h
Table 15-11. SDIOMSWRST Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENSTS R 0h
MMCHS_ENABLED_STATUS
0h = MMCHS clocks and resets are disabled
1h = MMCHS clocks and resets are enabled
0 SWRST R/W 0h
MMCHS_SOFT_RESET
0h = Deassert reset for MMCHS-core
1h = Assert reset for MMCHS-core
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