Texas Instruments CC3235 SimpleLink Series - DSLPTIMRCFG Register; DSLPTIMRCFG Register Field Descriptions

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.45 DSLPTIMRCFG Register (offset = 10Ch) [reset = 0h]
DSLPTIMRCFG is shown in Figure 15-48 and described in Table 15-48.
Figure 15-48. DSLPTIMRCFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMROPPCFG TIMRCFG
R/W-0h R/W-0h
Table 15-48. DSLPTIMRCFG Register Field Descriptions
Bit Field Type Reset Description
31-16 TIMROPPCFG R/W 0h
DSLP_WAKE_TIMER_OPP_CFG Configuration (in slow_clks) which
indicates when to request for OPP during deep-sleep exit
15-0 TIMRCFG R/W 0h
DSLP_WAKE_TIMER_WAKE_CFG Configuration (in slow_clks)
which indicates when to request for WAKE during deep-sleep exit