Texas Instruments CC3235 SimpleLink Series - MCASPCLKEN Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.4 MCASPCLKEN Register (offset = 14h) [reset = 0h]
MCASPCLKEN is shown in Figure 15-7 and described in Table 15-7.
Figure 15-7. MCASPCLKEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
NU1 DSLPCLKEN
R-0h R-0h
15 14 13 12 11 10 9 8
NU2 SLPCLKEN
R-0h R/W-0h
7 6 5 4 3 2 1 0
NU3 RUNCLKEN
R-0h R/W-0h
Table 15-7. MCASPCLKEN Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-17 NU1 R 0h
16 DSLPCLKEN R 0h
MCASP_DSLP_CLK_ENABLE
0h = Disable MCASP clock during deep-sleep mode
15-9 NU2 R 0h
8 SLPCLKEN R/W 0h
MCASP_SLP_CLK_ENABLE
0h = Disable MCASP clock during sleep mode
1h = Enable MCASP clock during sleep mode
7-1 NU3 R 0h
0 RUNCLKEN R/W 0h
MCASP_RUN_CLK_ENABLE
0h = Disable MCASP clock during run mode
1h = Enable MCASP clock during run mode