Texas Instruments CC3235 SimpleLink Series - SPI_SYSSTATUS Register

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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.2 SPI_SYSSTATUS Register (offset = 114h) [reset = 0h]
SPI_SYSSTATUS is shown in Figure 8-21 and described in Table 8-8.
This register provides status information about the module excluding the interrupt status information.
Figure 8-21. SPI_SYSSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETDONE
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-8. SPI_SYSSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 RESETDONE R 0h
Internal Reset Monitoring
0h (R) = Internal module reset is on-going
1h (R) = Reset completed