Texas Instruments CC3235 SimpleLink Series - SHAMD5_DIGEST_COUNT Register; SHAMD5_DIGEST_COUNT Register Field Descriptions

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SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.17 SHAMD5_DIGEST_COUNT Register (Offset = 40h) [reset = 0h]
SHAMD5_DIGEST_COUNT is shown in Figure 19-21 and described in Table 19-28.
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WRITE: Initial Digest Count ([31:6] only, [5:0] assumed 0)
READ: Result / IntermediateDigest Count
The initial digest byte count for hash/HMAC continue operations (HMAC key processing = 0 and use
algorithm constants = 0) on the secure world must be written to this register before starting the operation
by writing to S_HASH_MODE. When either HMAC key processing is 1 or use algorithm constants is 1,
this register does not need to be written, it is overwritten with 64 (1 hash block of key XOR ipad) or 0
respectively, automatically.
When starting an HMAC operation from pre-computes (HMAC key processing is 0), the value 64 must be
written here to compensate for the appended key XOR ipad block. The value written should always be a
64 byte multiple; the lower 6 bits written are ignored.
The updated digest byte count (initial digest byte count plus bytes processed) can be read from this
register when the status register indicates that the operation is done or suspended due to a context switch
request, or when a secure world context out DMA is requested.
Figure 19-21. SHAMD5_DIGEST_COUNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-28. SHAMD5_DIGEST_COUNT Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h
Data