Texas Instruments CC3235 SimpleLink Series - DMA_CHMAP0 Register

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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.19 DMA_CHMAP0 Register (offset = 510h) [reset = 0h]
DMA_CHMAP0 is shown in Figure 4-25 and described in Table 4-29.
Each 4-bit field of the DMACHMAP0 register configures the DMA channel assignment.
Figure 4-25. DMA_CHMAP0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH7SEL_n CH6SEL_n CH5SEL_n CH4SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3SEL_n CH2SEL_n CH1SEL_n CH0SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-29. DMA_CHMAP0 Register Field Descriptions
Bit Field Type Reset Description
31-28 CH7SEL_n R/W 0h
DMA channel 7 source select
27-24 CH6SEL_n R/W 0h
DMA channel 6 source select
23-20 CH5SEL_n R/W 0h
DMA channel 5 source select
19-16 CH4SEL_n R/W 0h
DMA channel 4 source select
15-12 CH3SEL_n R/W 0h
DMA channel 3 source select
11-8 CH2SEL_n R/W 0h
DMA channel 2 source select
7-4 CH1SEL_n R/W 0h
DMA channel 1 source select
3-0 CH0SEL_n R/W 0h
DMA channel 0 source select