Texas Instruments CC3235 SimpleLink Series - GPIOIEV Register; GPIOIEV Register Field Descriptions

GPIO Registers www.ti.com
166
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
General-Purpose Input/Outputs (GPIOs)
5.5.5 GPIOIEV Register (offset = 40Ch) [reset = 0h]
GPIOIEV is shown in Figure 5-8 and described in Table 5-8.
The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the
GPIO Interrupt Sense (GPIOIS) register. Clearing a bit configures the pin to detect falling edges or low
levels, depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset.
Figure 5-8. GPIOIEV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IEV
R-0h R/W-0h
Table 5-8. GPIOIEV Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 IEV R/W 0h
GPIO Interrupt Event
0h = A falling edge or a Low level on the corresponding pin triggers
an interrupt.
1h = A rising edge or a High level on the corresponding pin triggers
an interrupt.