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GPIO Registers
165
SWRU543–January 2019
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General-Purpose Input/Outputs (GPIOs)
5.5.4 GPIOIBE Register (offset = 408h) [reset = 0h]
GPIOIBE is shown in Figure 5-7 and described in Table 5-7.
The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register is set to detect edges, setting a bit in the GPIOIBE register configures
the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the
GPIO Interrupt Event (GPIOIEV) register. Clearing a bit configures the pin to be controlled by the
GPIOIEV register. All bits are cleared by a reset.
To prevent false interrupts, the following steps should be taken when reconfiguring GPIO edge and
interrupt sense registers:
1. Mask the corresponding port by clearing the IME field in the GPIOIM register.
2. Configure the IS field in the GPIOIS register and the IBE field in the GPIOIBE register.
3. Clear the GPIORIS register.
4. Unmask the port by setting the IME field in the GPIOIM register.
Figure 5-7. GPIOIBE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IBE
R-0h R/W-0h
Table 5-7. GPIOIBE Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 IBE R/W 0h
GPIO Interrupt Both Edges
0h = Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register.
1h = Both edges on the corresponding pin trigger an interrupt.
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