Texas Instruments CC3235 SimpleLink Series - DMA_SWREQ Register; DMA_SWREQ Register Field Descriptions

Register Description www.ti.com
138
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
4.3.4.6 DMA_SWREQ Register (offset = 14h) [reset = 0h]
DMA_SWREQ is shown in Figure 4-12 and described in Table 4-16.
Each bit in this register represents the corresponding DMA channel. Setting a bit generates a request for
the specified DMA channel.
Figure 4-12. DMA_SWREQ Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWREQ_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-16. DMA_SWREQ Register Field Descriptions
Bit Field Type Reset Description
31-0 SWREQ_n W 0h Channel [n] Software Request These bits generate software
requests.
Bit 0 corresponds to channel 0.
These bits are automatically cleared when the software request has
been completed.
0h = No request generated
1h = Generate a software request for the corresponding channel.