SPI_SCLK Edge Nr.
Sample
End
Begin
SPI_SCLK (POL = 0)
SPI_SCLK (POL = 1)
Data From the Master
Data From the Slave
Slave Select ( )
(optional)
SPI_SCS[n]
1 2
3
4
5
6
7
8 9 10
11 12
13
14
15 16
MSB
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
LSB
MSB
Bit6
Bit5
Bit4
Bit3
Bit2 Bit1
LSB
t
LEAD
t
LAG
Transfer
Functional Description
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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
Figure 8-5. Full-Duplex Single Transfer Format With PHA = 1
t
Lead
— Minimum leading time required for slave mode (ensured in master mode) before the first SPICLK
edge.
t
Lag
— Minimum trailing time required for slave mode (ensured in master mode) after the last SPICLK
edge.
In 3-pin mode without using the SPIEN signal, the controller provides the same waveform, with SPIEN
forced to low state. In 3-pin slave mode, SPIEN is useless.
8.2.3 Master Mode
The SPI is in master mode when the MS bit of the SPI_MODULCTRL register is cleared.
8.2.3.1 Interrupt Events in Master Mode
The interrupt events related to the transmitter register state are TX_empty and TX_underflow. The
interrupt event related to the receiver register state is RX_full.
8.2.3.1.1 TX_empty
The TX_empty event is activated when a channel is enabled and its transmitter register becomes empty
(transient event). Enabling the channel automatically raises this event. When the FIFO buffer is enabled
(MCSPI_CHCONF[FFEW] set to 1), the TX_empty event is asserted when there is enough space in the
buffer to write the number of bytes defined by MCSPI_XFERLEVEL[AEL].
The transmitter register must be loaded to remove the source of the interrupt, and the TX_empty interrupt
status bit must be cleared for interrupt line deassertion (if the event is enabled as an interrupt source).
When FIFO is enabled, no new TX_empty event is asserted when the local host has not performed the
number of writes into the transmitter register, defined by MCSPI_XFERLEVEL[AEL]. The local host must
perform the correct number of writes.
8.2.3.1.2 TX_underflow
The TX_underflow event is activated when the channel is enabled and the transmitter register or FIFO is
empty (not updated with new data) at the time of a shift register assignment. TX_underflow acts as a
warning in master mode.
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