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Functional Description
271
SWRU543–January 2019
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SPI (Serial Peripheral Interface)
To avoid having TX_underflow event at the beginning of a transmission, TX_underflow is not activated
when no data has been loaded into the transmitter register, because the channel has been enabled. To
avoid TX_underflow, the transmitter register must rarely be loaded. The TX_underflow interrupt status bit
must be cleared for interrupt line deassertion (if the event is enabled as an interrupt source).
8.2.3.1.3 RX_ full
Throughout: Are references to FFER and FFEW valid, or should they be FFRE and FFWE? (Figures
6 to 9 refer to FFRE and FFWE.)
The RX_full event is activated when the channel is enabled and the receiver register is filled. When the
FIFO buffer is enabled (MCSPI_CHCONF[FFER] set to 1), the RX_full event is asserted when a certain
number of bytes are held in the buffer to read, as defined by MCSPI_XFERLEVEL[AFL].
The receiver register must be read to remove the source of the interrupt, and the RX_full interrupt status
bit must be cleared for interrupt line deassertion (if the event is enabled as an interrupt source).
When FIFO is enabled, no new RX_full event is asserted if the local host has not performed the number of
reads into the receive register, as defined by MCSPI_XFERLEVEL[AFL]. The local host must perform the
correct number of reads.
8.2.3.1.4 End-of-Word Count
The EOW (end-of-word count) event is activated when the channel is enabled and configured to use the
built-in FIFO. This interrupt is raised when the controller performs the number of transfers defined in the
MCSPI_XFERLEVEL[WCNT] register. If the value was programmed to 0x0000, the counter is not
enabled, and this interrupt is not generated.
The EOW count interrupt also indicates that the SPI transfer is halted on the channel (using the FIFO
buffer) until MCSPI_XFERLEVEL[WCNT] is not reloaded and the channel is re-enabled. The EOW
interrupt status bit must be cleared for interrupt line deassertion (if the event is enabled as an interrupt
source).
8.2.3.2 Master Transmit and Receive Mode
The master transmit and receive mode is programmable by the TRM bit of the SPI_CHCONF register. The
channel access to the shift registers is based on its transmitter and receiver register state.
1. The channel can be scheduled for transmission or reception only when enabled (EN bit of the
SPI_CHCTRL register).
2. An enabled channel can be scheduled if its transmitter register is not empty (TXS bit of the
SPI_CHSTAT register) or its FIFO is not empty, or if the buffer is used (FFE bit of the
MCSPI_CHSTAT register) and updated with new data at the time of shift register assignment. If the
transmitter register or FIFO is empty at the time of shift register assignment, the TX_underflow event is
activated.
3. An enabled channel can be scheduled if its receive register is not full (RXS bit of the SPI_CHSTAT
register), or its FIFO is not full if the buffer is used (FFF bit of the MCSPI_CHSTAT register) at the time
of shift register assignment. Thus, the receiver register of FIFO cannot be overwritten. The
RX_overflow bit in the SPI_IRQSTATUS register is never set in this mode.
The built-in FIFO is available in this mode, and can be configured in one or both data directions for
transmit or receive. The FIFO is seen as a 64-byte buffer if configured for one data direction. If configured
in both data directions (transmit and receive), the FIFO is split into two separate 32-byte buffers with their
own address space management. In this case, the definition of the AEL and AFL levels is based on 32
bytes, and is the responsibility of the local host.
8.2.3.3 SPI Enable Control in Master Mode
When SPI is configured as a master device, the assertion of the SPIEN is optional, depending on the
device connected to the controller. The following is a description of each configuration:
• In 3-pin mode: the MCSPI_MODULCTRL[1] PIN34 and MCSPI_MODULCTRL[0] SINGLE bits are set
to 1, and the controller transmits the SPI word when the transmit register or FIFO is not empty.
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