I2C Registers
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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.17 I2CSIMR Register (Offset = 80Ch) [reset = 0h]
I2CSIMR is shown in Figure 7-30 and described in Table 7-21.
Return to Summary Table.
This register controls whether a raw interrupt is promoted to a controller interrupt.
Figure 7-30. I2CSIMR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFIM
R-0h R/W-0h
7 6 5 4 3 2 1 0
TXFEIM RXIM TXIM DMATXIM DMARXIM STOPIM STARTIM DATAIM
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-21. I2CSIMR Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 RXFFIM R/W 0h
Receive FIFO Full Interrupt Mask
0h = The RXFFRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = The Receive FIFO Full interrupt is sent to the interrupt
controller when the RXFFRIS bit in the I2CSRIS register is set.
7 TXFEIM R/W 0h
Transmit FIFO Empty Interrupt Mask
0h = The TXFERIS interrupt is suppressed and not sent to the
interrupt controller.
1h = The Transmit FIFO Empty interrupt is sent to the interrupt
controller when the TXFERIS bit in the I2CSRIS register is set.
6 RXIM R/W 0h
Receive FIFO Request Interrupt Mask
0h = The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
1h = The RX FIFO Request interrupt is sent to the interrupt controller
when the RXRIS bit in the I2CSRIS register is set.
5 TXIM R/W 0h
Transmit FIFO Request Interrupt
0h = The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
1h = The TX FIFO Request interrupt is sent to the interrupt controller
when the TXRIS bit in the I2CSRIS register is set.
4 DMATXIM R/W 0h
Transmit DMA Interrupt Mask
0h = The DMATXRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = The transmit DMA complete interrupt is sent to the interrupt
controller when the DMATXRIS bit in the I2CSRIS register is set.
3 DMARXIM R/W 0h
Receive DMA Interrupt Mask
0h = The DMARXRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = The receive DMA complete interrupt is sent to the interrupt
controller when the DMARXRIS bit in the I2CSRIS register is set.
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