Register Description
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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.2 DMA_CFG Register (offset = 4h) [reset = 0h]
DMA_CFG is shown in Figure 4-8 and described in Table 4-12.
This register contain configuration for DMA controller.
Figure 4-8. DMA_CFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MASTEN
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-12. DMA_CFG Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MASTEN R/W 0h
Controller Master enable
0h = Disables DMA controller
1h = Enables DMA controller
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