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Camera Registers
497
SWRU543–January 2019
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Parallel Camera Interface Module
14.6.1 CC_SYSCONFIG Register (Offset = 10h) [reset = 0h]
CC_SYSCONFIG is shown in Figure 14-9 and described in Table 14-4.
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This register controls the various parameters of the OCP interface (CCP and parallel mode).
Figure 14-9. CC_SYSCONFIG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SIdleMode RESERVED SoftReset AutoIdle
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-4. CC_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4-3 SIdleMode R/W 0h
Slave interface power management, req/ack control
00h = Force-idle. An idle request is acknowledged unconditionally.
01h = No-idle. An idle request is never acknowledged.
10h = Reserved (Smart-idle not implemented)
11h = Reserved – Do not use
2 RESERVED R/W 0h
1 SoftReset R/W 0h
Software reset
Set this bit to 1 to trigger a module reset. The bit is automatically
reset by the hardware. During reset it always returns 0.
0h = Normal mode
1h = The module is reset
0 AutoIdle R/W 0h
Internal OCP clock gating strategy
0h = OCP clock is free-running
1h = Automatic OCP clock gating strategy is applied, based on the
OCP interface activity
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