Texas Instruments CC3235 SimpleLink Series - DMA_PRIOCLR Register; DMA_PRIOCLR Register Field Descriptions

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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.16 DMA_PRIOCLR Register (offset = 3Ch) [reset = 0h]
DMA_PRIOCLR is shown in Figure 4-22 and described in Table 4-26.
Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding
SET[n] bit in the DMAPRIOSET register.
Figure 4-22. DMA_PRIOCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-26. DMA_PRIOCLR Register Field Descriptions
Bit Field Type Reset Description
31-0 CLR_n W 0h
Channel [n] Priority Clear
0h = No effect
1h = Setting a bit clears the corresponding SET[n] bit in the
DMAPRIOSET register meaning that channel [n] is using the default
priority level