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SHA-MD5 Registers
749
SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.40 DTHE_SHA_RIS Register (Offset = 814h) [reset = X]
DTHE_SHA_RIS is shown in Figure 19-44 and described in Table 19-51.
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SHAMD5 raw interrupt status register
Figure 19-44. DTHE_SHA_RIS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED Din Cout Cin
R-X R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-51. DTHE_SHA_RIS Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
2 Din R 0h
Input data movement is done
1 Cout R 0h
Context output is done
0 Cin R 0h
Context input is done
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