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WATCHDOG Registers
353
SWRU543–January 2019
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Watchdog Timer
10.3.3 WDTCTL Register (offset = 8h) [reset = 80000000h]
WDTCTL is shown in Figure 10-4 and described in Table 10-4.
This register is the watchdog control register. The watchdog timer WDT?can be used to generate a reset
signal (on the second time-out) or an interrupt on the first? time-out.
Figure 10-4. WDTCTL Register
31 30 29 28 27 26 25 24
WRC RESERVED
R-1h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INTTYPE RESERVED INTEN
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 10-4. WDTCTL Register Field Descriptions
Bit Field Type Reset Description
31 WRC R 1h Write Complete
The WRC values are defined as follows: Note: This bit is reserved
for WDT0 and has a reset value of 0.
0h = A write access to one of the WDT1 registers is in progress.
1h = A write access is not in progress, and WDT1 registers can be
read or written.
30-3 RESERVED R 0h
2 INTTYPE R/W 0h
Watchdog Interrupt Type. The INTTYPE values are defined as
follows:
0h = Watchdog interrupt is a standard interrupt.
1h = Not Valid Value
1 RESERVED R/W 0h
0 INTEN R/W 0h
Watchdog Interrupt Enable. The INTEN values are defined as
follows:
0h = Interrupt event disabled (when this bit is set, it can only be
cleared by a hardware reset).
1h = Interrupt event enabled. Once enabled, all writes are ignored.
Setting this bit enables the WDT.
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