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SWRU543–January 2019
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Cortex
®
-M4 Peripherals
3.3.1.7 PEND_0 to PEND_6 Register (offset = 200h to 218h) [reset = 0h]
PEND_0 to PEND_6 is shown in Figure 3-7 and described in Table 3-10.
The PENDn registers force interrupts into the pending state and show which interrupts are pending. Bit 0
of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1 corresponds to
Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to Interrupt 64; bit 31
corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt
127. Bit 0 of PEND4 corresponds to Interrupt 128; bit 31 corresponds to Interrupt 159. Bit 0 of PEND5
corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of PEND6 corresponds to Interrupt
192; bit 7 corresponds to Interrupt 199.
NOTE: This register can only be accessed from privileged mode.
Figure 3-7. PEND_0 to PEND_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-10. PEND_0 to PEND_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Set Pending
If the corresponding interrupt is already pending, setting a bit has no
effect. A bit can only be cleared by setting the corresponding INT[n]
bit in the UNPEND0 (for PEND0 to PEND3) register.
UNPEND4 (for PEND4) register
UNPEND5 (for PEND5) register
UNPEND6 (for PEND6) register
0h (W) = On a write, no effect.
0h (R) = On a read, indicates that the interrupt is not pending.
1h (W) = On a write, the corresponding interrupt is set to pending
even if it is disabled.
1h (R) = On a read, indicates that the interrupt is pending.
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