Texas Instruments CC3235 SimpleLink Series - I2 CMBMON Register; I2 CMBMON Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.11 I2CMBMON Register (Offset = 2Ch) [reset = 3h]
I2CMBMON is shown in Figure 7-24 and described in Table 7-15.
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This register is used to determine the SCL and SDA signal status.
Figure 7-24. I2CMBMON Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SDA SCL
R-0h R-1h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-15. I2CMBMON Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 SDA R 1h
I2C SDA Status
0h = The I2CSDA signal is low.
1h = The I2CSDA signal is high.
0 SCL R 1h
I2C SCL Status
0h = The I2CSCL signal is low.
1h = The I2CSCL signal is high.