Texas Instruments CC3235 SimpleLink Series - DES_IRQSTATUS Register

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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5.18 DES_IRQSTATUS Register (Offset = 103Ch) [reset = 0h]
DES_IRQSTATUS is shown in Figure 18-25 and described in Table 18-25.
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This register indicates the interrupt status. If one of the interrupt bits is set, the interrupt output is asserted.
Figure 18-25. DES_IRQSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
RO-0h
23 22 21 20 19 18 17 16
RESERVED
RO-0h
15 14 13 12 11 10 9 8
RESERVED
RO-0h
7 6 5 4 3 2 1 0
RESERVED DATA_OUT DATA_IN CONTEX_IN
RO-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-25. DES_IRQSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED RO 0h
2 DATA_OUT R/W 0h
This bit indicates data output interrupt is active and triggers the
interrupt output.
1 DATA_IN R/W 0h
This bit indicates data input interrupt is active and triggers the
interrupt output.
0 CONTEX_IN R/W 0h
This bit indicates context interrupt is active and triggers the interrupt
output.