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SWRU543–January 2019
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Cortex
®
-M4 Peripherals
3.3.1.11 CPUID Register (Offset = D00h) [reset = 410FC241h]
CPUID is shown in Figure 3-11 and described in Table 3-14.
Return to Summary Table.
The CPUID register contains the ARM Cortex-M4 processor part number, version, and implementation
information.
NOTE: This register can only be accessed from privileged mode.
Figure 3-11. CPUID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMP VAR CON PARTNO REV
R-41h R-0h R-Fh R-C24h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-14. CPUID Register Field Descriptions
Bit Field Type Reset Description
31-24 IMP R 41h
Implementer Code
41h = ARM
23-20 VAR R 0h
Variant Number
0h = The rn value in the rnpn product revision identifier, for example,
the 0 in r0p0.
19-16 CON R Fh
Constant Value Description 0xF Always reads as 0xF.
15-4 PARTNO R C24h
Part Number
C24h = Cortex-M4 application processor in CC32xx.
3-0 REV R 1h
Revision Number
1h = The pn value in the rnpn product revision identifier; for
example, the 1 in r0p1.
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