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I2C Registers
231
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.5 I2CMIMR Register (Offset = 10h) [reset = 0h]
I2CMIMR is shown in Figure 7-18 and described in Table 7-9.
Return to Summary Table.
This register controls whether a raw interrupt is promoted to a controller interrupt.
Figure 7-18. I2CMIMR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFIM TXFEIM RXIM TXIM
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
ARBLOSTIM STOPIM STARTIM NACKIM DMATXIM DMARXIM CLKIM IM
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-9. I2CMIMR Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h
11 RXFFIM R/W 0h
Receive FIFO Full Interrupt Mask
0h = The RXFFRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = The Receive FIFO Full interrupt is sent to the interrupt
controller when the RXFFRIS bit in the I2CMRIS register is set.
10 TXFEIM R/W 0h
Transmit FIFO Empty Interrupt Mask
Note: The TXFEIM interrupt mask bit in the I2CMIMR register should
be clear (masking the TXFE interrupt) when the master is performing
an RX Burst from the RXFIFO and should be unmasked before
starting a TX FIFO transfers.
0h = The TXFERIS interrupt is suppressed and not sent to the
interrupt controller.
1h = The Transmit FIFO Empty interrupt is sent to the interrupt
controller when the TXFERIS bit in the I2CMRIS register is set.
9 RXIM R/W 0h
Receive FIFO Request Interrupt Mask
0h = The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
1h = The RX FIFO Request interrupt is sent to the interrupt controller
when the RXRIS bit in the I2CMRIS register is set.
8 TXIM R/W 0h
Transmit FIFO Request Interrupt Mask
0h = The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
1h = The TX FIFO Request interrupt is sent to the interrupt controller
when the TXRIS bit in the I2CMRIS register is set.
7 ARBLOSTIM R/W 0h
Transmit FIFO Request Interrupt Mask
0h = The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
1h = The TX FIFO Request interrupt is sent to the interrupt controller
when the TXRIS bit in the I2CMRIS register is set.
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