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Camera Registers
507
SWRU543–January 2019
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Parallel Camera Interface Module
14.6.8 CC_FIFODATA Register (Offset = 4Ch) [reset = X]
CC_FIFODATA is shown in Figure 14-16 and described in Table 14-11.
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This register allows the user to write and read from the FIFO (CCP and parallel mode). Refer to
Section 14.3.2 for details about FIFO write and read accesses into this register bank.
Figure 14-16. CC_FIFODATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_DATA
R/W-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-11. CC_FIFODATA Register Field Descriptions
Bit Field Type Reset Description
31-0 FIFO_DATA R/W X
Reads or writes the 32-bit word from or into the FIFO.
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