Functional Description
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SWRU543–January 2019
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Parallel Camera Interface Module
NOTE: The module automatically removes the blanking period.
14.3.2 FIFO Buffer
The internal data FIFO buffer is 32 bits wide and 64 locations deep. Received data from the 8-bit parallel
interface is stored in the buffer until read out by the CPU, which accesses the buffer by reading locations
starting at the CC_FIFO_DATA register. When enabled, the buffer can generate DMA requests based on
the value of FIFO_CTRL_DMA.THRESHOLD.
The FIFO goes into overflow when a write is attempted to a full FIFO, because the software is too slow or
the throughput is too high. The content of the full FIFO is not corrupted by any further writes. During FIFO
overflow, it is still possible to read data from the FIFO. When the FIFO is no longer full, more writes are
possible.
The FIFO goes into underflow when a read is attempted from an empty FIFO, due to software (too many
read accesses). After an underflow, it is still possible to write. When the FIFO is no longer empty, it is
possible to read from FIFO.
The FIFO is reset by writing 1 into CC_CTRL.CC_RST. If FIFO_OF_IRQ (or FIFO_UF_IRQ) is enabled,
an overflow (or an underflow) generates an interrupt. The interrupt is cleared by writing 1 to the
FIFO_OF_IRQ bit (or FIFO_UF_IRQ), it is not necessary to apply CC_RST beforehand.
14.3.3 Reset
The camera core has two types of reset:
• Reset the Camera Core – Reset the camera core module globally by setting the
CC_SYSCONFIG.SoftReset bit to 1.
• Reset the FIFOs and DMA control – The internal state machines of the FIFO and the DMA control
circuitry are reset by setting the CC_CTRL.CC_RST bit to 1. This bit is primarily used after an
underflow or an overflow, to avoid reconfiguring the entire module.
14.3.4 Clock Generation
The module divides down CAM_MCLK and generates CAM_XCLK clock to the external camera sensor.
The configuration of the CAM_XCLK divider is programmable by setting the configuration register
CC_CTRL_XCLK.
CAM_XCLK is not used by the camera core module; it is routed to the chip pin. Table 14-2 lists the ratio of
the XCLK frequency generator.
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