Texas Instruments CC3235 SimpleLink Series - STCTRL Register; STCTRL Register Field Descriptions

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SWRU543–January 2019
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3.3.1.2 STCTRL Register (Offset = 10h) [reset = 0h]
STCTRL is shown in Figure 3-2 and described in Table 3-5.
Return to Summary Table.
The SysTick (STCTRL) register enables the SysTick features.
NOTE: This register can only be accessed from privileged mode.
Figure 3-2. STCTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED COUNT
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLK_SRC INTEN ENABLE
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-5. STCTRL Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 COUNT R 0h
Count Flag
This bit is cleared by a read of the register or if the STCURRENT
register is written with any value. If read by the debugger using the
DAP, this bit is cleared only if the MasterType bit in the AHB-AP
Control Register is clear. Otherwise, the COUNT bit is not changed
by the debugger read. See the ARM Debug Interface V5 Architecture
Specification for more information on MasterType.
0h = The SysTick timer has not counted to 0 since the last time this
bit was read.
1h = The SysTick timer has counted to 0 since the last time this bit
was read.
15-3 RESERVED R 0h
2 CLK_SRC R/W 0h
Clock Source
0h = Precision internal oscillator (PIOSC) divided by 4
1h = System clock
1 INTEN R/W 0h
Interrupt Enable
0h = Interrupt generation is disabled. Software can use the COUNT
bit to determine if the counter has ever reached 0.
1h = An interrupt is generated to the NVIC when SysTick counts to
0.
0 ENABLE R/W 0h
Enable
0h = The counter is disabled.
1h = Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down. On
reaching 0, the COUNT bit is set and an interrupt is generated if
enabled by INTEN. The counter then loads the RELOAD value again
and begins counting.