I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.26 XEVTCTL Register (Offset = CCh) [reset = 0h]
XEVTCTL is shown in Figure 12-29 and described in Table 12-31.
Return to Summary Table.
CAUTION
Accessing XEVTCTL when not implemented on a specific DSP may cause
improper device operation.
Figure 12-29. XEVTCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED XDATDMA
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-31. XEVTCTL Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
0 XDATDMA R/W 0h
Transmit data DMA request enable bit. If writing to this field, always
write the default value of 0.
0h = Transmit data DMA request is enabled.
1h = Reserved.
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