SHA-MD5 Registers
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SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.37 SHAMD5_IRQSTATUS Register (Offset = 118h) [reset = X]
SHAMD5_IRQSTATUS is shown in Figure 19-41 and described in Table 19-48.
Return to Summary Table.
Figure 19-41. SHAMD5_IRQSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED CONTEXT_RE
ADY
PARTHASH_R
EADY
INPUT_READY OUTPUT_REA
DY
R-X RO-1h RO-0h RO-0h RO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-48. SHAMD5_IRQSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R X
3 CONTEXT_READY RO 1h
Indicates that the secure-side context input registers are available for
a new context for the next packet to be processed.
2 PARTHASH_READY RO 0h
After a secure-side context switch request, this bit reads as 1,
indicating that the saved context is available from the secure-side
context output registers. If the context switch request coincides with
a final hash (when hashing) or an outer hash (when doing HMAC),
that PartHashReady will not become active, but a regular output
ready occurs instead (indicating that the result is final and therefore
no continuation is required).
1 INPUT_READY RO 0h
Indicates that the secure-side data FIFO is ready to receive the next
64-byte data block.
0 OUTPUT_READY RO 0h
Indicates that a (partial) result or saved context is available from the
secure-side context output registers.
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