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SWRU543–January 2019
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-M4 Peripherals
3.3.1.24 SWTRIG Register (Offset = F00h) [reset = 0h]
SWTRIG is shown in Figure 3-24 and described in Table 3-27.
Return to Summary Table.
Writing an interrupt number to the SWTRIG register generates a software-generated interrupt (SGI). When
the MAINPEND bit in the Configuration and Control (CFGCTRL) register is set, unprivileged software can
access the SWTRIG register.
NOTE: Only privileged software can enable unprivileged access to the SWTRIG register.
Figure 3-24. SWTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED INTID
R-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-27. SWTRIG Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 INTID W 0h
Interrupt ID
This field holds the interrupt ID of the required SGI. For example, a
value of 0x3 generates an interrupt on IRQ3.
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