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Timer Registers
341
SWRU543–January 2019
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General-Purpose Timers
9.5.17 GPTMTAR Register (offset = 48h) [reset = FFFFFFFFh]
GPTMTAR is shown in Figure 9-21 and described in Table 9-25.
When a GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit register (the
upper 16 bits correspond to the contents of the GPTM Timer B (GPTMTBR) register). In the 16-bit input
edge-count, input edge-time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16
contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To
read the value of the prescaler in 16-bit one-shot and periodic modes, read bits [23:16] in the GPTMTAV
register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale
Snapshot (GPTMTAPS) register.
Figure 9-21. GPTMTAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
R-FFFFFFFFh
Table 9-25. GPTMTAR Register Field Descriptions
Bit Field Type Reset Description
31-0 TAR R FFFFFFFFh
GPTM Timer A Register. A read returns the current value of the
GPTM Timer A Count register, in all cases except for input edge-
count and time modes. In the input edge-count mode, this register
contains the number of edges that have occurred. In the input edge-
time mode, this register contains the time at which the last edge
event took place.
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