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Pin Mapping Recommendations
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SWRU543–January 2019
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I/O Pads and Pin Multiplexing
16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
Table 16-12 describes the register fields of the GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32
registers.
Table 16-12. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description
Bit Field Type Reset Description
31-12 Reserved R 0
11-0 MEM_GPIO_PAD_CONFIG RW 0xC61
bit[3:0] CONFMODE. Determines which functional signal is routed to the
pad. Refer to the pin mux table.
bit[4] Enable open-drain mode (for example, when used as I2C).
bit[7:5] DRIVESTRENGTH:
011 = 6 mA
010 = 4 mA
001 = 2 mA
000 = Output driver not enabled
bit[8] Enable internal weak pullup.
bit[9] Enable internal weak pulldown.
bit[10] Pad output enable override value. Level enables the pad output
buffer. Otherwise, the output buffer is placed in a tristate condition This
does not affect the internal pullup or pulldown, which are controlled
independently by bit 8 and bit 9.
bit[11] This enables overriding of the pad output buffer enable. When this
bit is set to logic 1, the value in bit 4 controls the state of the pad output
buffer.
When this bit is set to logic 0, the state of the pad output buffer is directly
controlled by the peripheral module to which the pad is functionally muxed.
16.8.2 PAD Behavior During Reset and Hibernate
By default, all digital pads are Hi-Z during forced reset (nRESET=0) and hibernate. This includes the
serial-flash and JTAG pins.
On exit from chip reset or hibernate, the SPI-Flash pads and JTAG pads are configured automatically by
the resident ROM firmware during device initialization. The ROM bootloader then reads the application
image from the external SPI flash, loads it into SRAM, and makes a jump. At this point, all other digital
I/Os are in the reset default state (Hi-Z). The application code must configure the I/Os. The application
code must also configure any associated analog muxes for pins that are shared by both digital and analog
or PM functions.
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