I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.10 AFSRCTL Register (Offset = 6Ch) [reset = 0h]
AFSRCTL is shown in Figure 12-13 and described in Table 12-15.
Return to Summary Table.
The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR).
Figure 12-13. AFSRCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RMOD
R/W-0h
7 6 5 4 3 2 1 0
RMOD RESERVED FRWID RESERVED FSRM FSRP
R/W-0h R-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-15. AFSRCTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
15-7 RMOD R/W 0h
Receive frame sync mode select bits.
0h = Reserved
1h = Reserved
2h = 2-slot TDM (I2S mode)
6-5 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
4 FRWID R/W 0h
Receive frame sync width select bit indicates the width of the receive
frame sync (AFSR) during its active period.
0h = Reserved
1h = Single word
3-2 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
1 FSRM R/W 0h
Receive frame sync generation select bit.
0h = Externally-generated receive frame sync
1h = Internally-generated receive frame sync
0 FSRP R/W 0h
Receive frame sync polarity select bit.
0h = Reserved
1h = A falling edge on receive frame sync (AFSR) indicates the
beginning of a frame.