UART Registers
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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.9 UARTIM Register (Offset = 38h) [reset = 0h]
UARTIM is shown in Figure 6-11 and described in Table 6-11.
Return to Summary Table.
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows
the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the
raw interrupt signal from being sent to the interrupt controller.
Figure 6-11. UARTIM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DMATXIM DMARXIM
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED 9BITIM RESERVED OEIM BEIM PEIM
R-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
FEIM RTIM TXIM RXIM DSRIM DCDIM CTSIM RIIM
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-11. UARTIM Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 DMATXIM R/W 0h
Transmit DMA Interrupt Mask
0h = The DMATXRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = An interrupt is sent to the interrupt controller when the
DMATXRIS bit in the UARTRIS register is set.
16 DMARXIM R/W 0h
Receive DMA Interrupt Mask
0h = The DMARXRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = An interrupt is sent to the interrupt controller when the
DMARXRIS bit in the UARTRIS register is set.
15-13 RESERVED R 0h
12 9BITIM R/W 0h
Reserved
11 RESERVED R 0h
10 OEIM R/W 0h
UART Overrun Error Interrupt Mask
0h = The OERIS interrupt is suppressed and not sent to the interrupt
controller.
1h = An interrupt is sent to the interrupt controller when the OERIS
bit in the UARTRIS register is set.
9 BEIM R/W 0h
UART Break Error Interrupt Mask
0h = The BERIS interrupt is suppressed and not sent to the interrupt
controller.
1h = An interrupt is sent to the interrupt controller when the BERIS
bit in the UARTRIS register is set.
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