Texas Instruments CC3235 SimpleLink Series - SDIOMCLKCFG Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.6 SDIOMCLKCFG Register (offset = 20h) [reset = 0h]
SDIOMCLKCFG is shown in Figure 15-9 and described in Table 15-9.
Figure 15-9. SDIOMCLKCFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DIVOFFTIM NU1 DIVONTIM
R-0h R/W-0h R-0h R/W-0h
Table 15-9. SDIOMCLKCFG Register Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10-8 DIVOFFTIM R/W 0h
MMCHS_PLLCKDIV_OFF_TIME Configuration of OFF-TIME for
dividing PLL clock (240 MHz) in generation of MMCHS func-clk:
000h = 1
001h = 2
010h = 3
011h = 4
100h = 5
101h = 6
110h = 7
111h = 8
7-3 NU1 R 0h
2-0 DIVONTIM R/W 0h
MMCHS_PLLCKDIV_ON_TIME Configuration of ON-TIME for
dividing PLL clock (240 MHz) in generation of MMCHS func-clk:
000h = 1
001h = 2
010h = 3
011h = 4
100h = 5
101h = 6
110h = 7
111h = 8