I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
Table 12-4. I2S Registers Accessed Through DMA Port
Hex Address Register Name Register Description
Read Accesses RBUF
Receive buffer DMA port address. Cycles through receive
serializers, skipping over transmit serializers and inactive
serializers. Starts at the lowest serializer at the beginning of
each time slot. Reads from DMA port only if XBUSEL = 0 in
XFMT.
Write Accesses XBUF
Transmit buffer DMA port address. Cycles through transmit
serializers, skipping over receive and inactive serializers. Starts
at the lowest serializer at the beginning of each time slot. Writes
to DMA port only if RBUSEL = 0 in RFMT.
Table 12-5. I2S AFIFO Registers Accessed Through Peripheral Configuration Port
Offset Acronym Register Section
0h AFIFOREV
AFIFO revision identification
register
Section 12.5.1
10h WFIFOCTL Write FIFO control register Section 12.5.2
14h WFIFOSTS Write FIFO status register
18h RFIFOCTL Read FIFO control register Section 12.5.4
1Ch RFIFOSTS Read FIFO status register Section 12.5.5
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