Texas Instruments CC3235 SimpleLink Series - SHAMD5_IRQENABLE Register

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SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.38 SHAMD5_IRQENABLE Register (Offset = 11Ch) [reset = X]
SHAMD5_IRQENABLE is shown in Figure 19-42 and described in Table 19-49.
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The SHAMD5_IRQENABLE register contains an enable bit for each unique interrupt for the public side.
An interrupt is enabled when both the global enable in SHAMD5_SYSCONFIG (PIT_en) and the bit in this
register are both set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_P output. The
dedicated partial hash output (SINTREQUEST_PART_P) is not affected by this register, it is only affected
by the global enable SHAMD5_SYSCONFIG (PIT_en).
Figure 19-42. SHAMD5_IRQENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED M_CONTEXT_
READY
M_PARTHASH
_READY
M_INPUT_REA
DY
M_OUTPUT_R
EADY
R-X R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-49. SHAMD5_IRQENABLE Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R X
3 M_CONTEXT_READY R/W 0h
Mask for context ready
2 M_PARTHASH_READY R/W 0h
Mask for partial hash
1 M_INPUT_READY R/W 0h
Mask for input_ready
0 M_OUTPUT_READY R/W 0h
Mask for output_ready