PRCM Registers
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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.26 UART0CLKEN Register (offset = 80h) [reset = 0h]
UART0CLKEN is shown in Figure 15-29 and described in Table 15-29.
Figure 15-29. UART0CLKEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED UART0DSLPC
LKEN
R-0h R/W-0h
15 14 13 12 11 10 9 8
NU1 UART0SLPCLK
EN
R-0h R/W-0h
7 6 5 4 3 2 1 0
NU2 UART0RCLKE
N
R-0h R/W-0h
Table 15-29. UART0CLKEN Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 UART0DSLPCLKEN R/W 0h
UART_A0_DSLP_CLK_ENABLE
0h = Disable UART_A0 clock during deep-sleep mode
1h = Enable UART_A0 clock during deep-sleep mode
15-9 NU1 R 0h
8 UART0SLPCLKEN R/W 0h
UART_A0_SLP_CLK_ENABLE
0h = Disable UART_A0 clock during sleep mode
1h = Enable UART_A0 clock during sleep mode
7-1 NU2 R 0h
0 UART0RCLKEN R/W 0h
UART_A0_RUN_CLK_ENABLE
0h = Disable UART_A0 clock during run mode
1h = Enable UART_A0 clock during run mode
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