EasyManua.ls Logo

Texas Instruments CC3235 SimpleLink Series - Summary of Processor Mode, Privilege Level, and Stack Use

Texas Instruments CC3235 SimpleLink Series
799 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Functional Description
www.ti.com
54
SWRU543January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Processor
2.2 Functional Description
2.2.1 Programming Model
This section describes the Cortex
®
-M4 programming model and includes the individual core register
descriptions, information about the processor modes, and privilege levels for software execution and
stacks.
2.2.1.1 Processor Mode and Privilege Levels for Software Execution
The Cortex
®
-M4 has two modes of operation:
Thread mode to execute application software. The processor enters thread mode when it comes out of
reset.
Handler mode to handle exceptions. When the processor has finished exception processing, it returns
to thread mode.
In addition, the Cortex
®
-M4 has two privilege levels:
Unprivileged: In this mode, the software has the following restrictions:
Limited access to the MSR and MRS instructions, and no use of the CPS instruction
No access to the system timer, NVIC, or system control block
Possibly restricted access to memory or peripherals
Privileged: In this mode, the software can use all instructions and has access to all resources
In thread mode, the CONTROL register controls whether software execution is privileged or unprivileged.
In handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to
transfer control to privileged software.
2.2.1.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item
on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer,
then writes the item to the new memory location. The processor implements two stacks: the main stack
and the process stack, with a pointer for each held in independent registers (see the SP register).
In thread mode, the CONTROL register controls whether the processor uses the main stack or the
process stack. In handler mode, the processor always uses the main stack. Table 2-1 lists the options for
processor operations.
(1)
See the CONTROL register in Section 2.2.2.2.8.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode Use Privilege Level Stack Used
Thread Applications Privileged or unprivileged
(1)
Main stack or process stack
(1)
Handler Exception handlers Always privileged Main stack

Table of Contents

Related product manuals