Functional Description
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SWRU543–January 2019
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Cortex
®
-M4 Processor
2.2.2.2.7 Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a
nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the
BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This
register is accessible only in privileged mode.
2.2.2.2.8 Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when the
processor is in thread mode, and indicates whether the FPU state is active. This register is accessible only
in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value. In an OS environment, threads running
in thread mode should use the process stack, and the kernel and exception handlers should use the main
stack. By default, thread mode uses the MSP. To switch the stack pointer used in thread mode to the
PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex
®
-M4 Devices Generic
User Guide (ARM DUI 0553A), or perform an exception return to thread mode with the appropriate
EXC_RETURN value.
NOTE: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex
®
-M4 Devices Generic User Guide (ARM DUI 0553A).
2.2.2.3 Exceptions and Interrupts
The Cortex
®
-M4 application processor in the CC32xx supports interrupts and system exceptions. The
processor and the NVIC prioritize and handle all exceptions. An exception changes the normal flow of
software control. The processor uses handler mode to handle all exceptions except for reset. See
Section 2.2.4.7 for more information.
The NVIC registers control interrupt handling. See Section 3.2.2 for more information.
2.2.2.4 Data Types
The Cortex
®
-M4 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-
bit data transfer instructions. All instruction and data memory accesses are little endian.
2.2.3 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding
features. The processor has a fixed memory map that provides up to 4GB of addressable memory.
Table 2-4 provides the memory map of the CC32xx microcontroller subsystem. In this manual, register
addresses are given as a hexadecimal increment, relative to the base address of the module, as shown in
the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to
bit data (see Section 2.2.3.1).
The processor reserves regions of the private peripheral bus (PPB) address range for core peripheral
registers (see Chapter 3).
NOTE: Within the memory map, attempts to read or write addresses in reserved spaces result in a
bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault.
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