Texas Instruments CC3235 SimpleLink Series - GPIO3 SWRST Register

www.ti.com PRCM Registers
551
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Power, Reset, and Clock Management
15.6.21 GPIO3SWRST Register (offset = 6Ch) [reset = 0h]
GPIO3SWRST is shown in Figure 15-24 and described in Table 15-24.
Figure 15-24. GPIO3SWRST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENSTS SWRST
R-0h R-0h R/W-0h
Table 15-24. GPIO3SWRST Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENSTS R 0h
GPIO_D_ENABLED_STATUS
0h = GPIO_D clocks and resets are disabled
1h = GPIO_D clocks and resets are enabled
0 SWRST R/W 0h
GPIO_D_SOFT_RESET
0h = Deassert reset for GPIO_D
1h = Assert reset for GPIO_D