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I2C Registers
245
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.15 I2CSCSR Register (Offset = 804h) [reset = 0h]
I2CSCSR is shown in Figure 7-28 and described in Table 7-19.
Return to Summary Table.
This register functions as a control register when written, and a status register when read.
Figure 7-28. I2CSCSR Register
31 30 29 28 27 26 25 24
ACTDMARX ACTDMATX RESERVED
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED QCMDRW QCMDST OAR2SEL FBR_OR_RXFI
FO
TREQ_OR_TX
FIFO
RREQ_OR_DA
R-0h RC-0h RC-0h RO-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-19. I2CSCSR Register Field Descriptions
Bit Field Type Reset Description
31 ACTDMARX R 0h
DMA RX Active Status
0h (R) = DMA RX is not active
1h (R) = DMA RX is active.
30 ACTDMATX R 0h
DMA RX Active Status
0h (R) = DMA RX is not active
1h (R) = DMA RX is active.
29-6 RESERVED R 0h
5 QCMDRW RC 0h
Quick Command Read / Write
This bit only has meaning when the QCMDST bit is set.
0h (R) = Quick command was a write
1h (R) = Quick command was a read
4 QCMDST RC 0h
Quick Command Status
0h (R) = The last transaction was a normal transaction or a
transaction has not occurred.
1h (R) = The last transaction was a Quick Command transaction.
3 OAR2SEL RO 0h
OAR2 Address Matched
This bit is reevaluated after every address comparison.
0h (R) = Either the address is not matched or the match is in legacy
mode.
1h (R) = OAR2 address matched and ACKed by the slave.
2 FBR_OR_RXFIFO R/W 0h
First Byte Received (R) or RX FIFO Enable
This bit is only valid when the RREQ bit is set and is automatically
cleared when data has been read from the I2CSDR register.
0h (W) = Disables RX FIFO
0h (R) = The first byte has not been received.
1h (W) = Enables RX FIFO
1h (R) = The first byte following the slave s own address has been
received.
Note: This bit is not used for slave transmit operations.