Analog and Digital Pin Multiplexing
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SWRU543–January 2019
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I/O Pads and Pin Multiplexing
NOTE: TI recommends using the lowest possible drive-strength that is adequate for the applications.
This minimizes the risk of interference to WLAN radio and mitigates any potential
degradation of RF sensitivity and performance. The default drive-strength setting is 6 mA.
16.3 Analog and Digital Pin Multiplexing
The CC32xx device implements an advanced analog and digital pin multiplexing scheme to maximize the
number of functional signals in a compact 64-pin QFN package. Pins are multiplexed with analog-test,
RF-test, clock and power-management functionalities. This is shown in Figure 16-1.
Section 16.5 describes the control registers for the analog signal mux and switches (S1 to S10 in
Figure 16-1).
16.4 Special Analog/Digital Pins
16.4.1 Pins 45 and 52
Pin 45 and pin 52 are used by an internal DC/DC (ANA2_DCDC) and the RTC crystal oscillator,
respectively. These modules use automatic configuration sensing. Thus, some board-level configuration is
required to use pin 45 and pin 52 as digital pads. Figure 16-2 shows this board-level configuration.
NOTE: In a CC32xxR device, ANA2 DC/DC is not required, which allows use of pins for digital
functions. However, pin 47 must be shorted to the supply input.
Typically, pin 52 is used up for RTC crystal in most applications. In some applications, however, a 32.768-
kHz square-wave clock may be available onboard. In such cases, the crystal may be removed, freeing up
pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically
detect this configuration, a 100K pullup resistor must be connected between pin 52 and the supply line. To
prevent false detection, TI recommends using pin 52 for output-only functionalities.
16.4.2 Pins 29 and 30
Pins 29 and 30 are reserved for WLAN antenna diversity. These pins control an external RF switch, which
multiplexes the RF pin of the CC32xx between two antennas. Do not use these pins for other functions.
16.4.3 Pins 57, 58, 59, and 60
These pins are shared by the ADC inputs and digital I/O pad cells.
NOTE: The ADC inputs are tolerant up to 1.8 V. The digital pads, on the other hand, can swing up
to 3.63 V. Thus, take care to prevent accidental damage to the ADC inputs. TI recommends
first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel
(for example, make them Hi-Z). Thereafter, the respective pass switches (S7 to S10) should
be enabled.
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