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SHA-MD5 Registers
745
SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.36 SHAMD5_SYSCONFIG Register (Offset = 110h) [reset = X]
SHAMD5_SYSCONFIG is shown in Figure 19-40 and described in Table 19-47.
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Figure 19-40. SHAMD5_SYSCONFIG Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED PCONT_SWT RESERVED PDMA_EN PIT_EN RESERVED
R-X R/W-0h R-X R/W-0h R/W-0h R-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-47. SHAMD5_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R X
6 PCONT_SWT R/W 0h
Finishes all pending data and context DMA input requests (but will
not assert any new requests), finishes processing all data in the
module, and provides a saved context (partial hash result, updated
digest count, remaining length, updated mode information where
applicable) for the last operation that was interrupted, so that it can
be resumed later.
5-4 RESERVED R X
3 PDMA_EN R/W 0h
Enable DMA
0h = DMA disabled
1h = DMA enabled
2 PIT_EN R/W 0h
Enable Interrupt
0h = Interrupt disabled
1h = Interrupt enabled
1-0 RESERVED R X
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