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I2C Registers
243
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.13 I2CMBCNT Register (Offset = 34h) [reset = 0h]
I2CMBCNT is shown in Figure 7-26 and described in Table 7-17.
Return to Summary Table.
When BURST is active, the value in the I2CMBLEN register is copied into this register and decremented
during the BURST transaction. This register can be used to determine the number of transfers that
occurred when a BURST terminates early (as a result of a data NACK). When a BURST completes
successfully, this register will contain 0.
Figure 7-26. I2CMBCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CNTL
R-0h Ro-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-17. I2CMBCNT Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 CNTL Ro 0h
I2C Master Burst Count
This field contains the current count-down value of the BURST
transaction.
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