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I2S Registers
427
SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.8 RMASK Register (Offset = 64h) [reset = 0h]
RMASK is shown in Figure 12-11 and described in Table 12-13.
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The receive format unit bit mask register (RMASK) determines which bits of the received data are masked
off and padded with a known value before being read by the CPU or DMA.
Figure 12-11. RMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMASK[31-0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-13. RMASK Register Field Descriptions
Bit Field Type Reset Description
31-0 RMASK[31-0] R/W 0h
Receive data mask enable bit.
0h = Corresponding bit of receive data (after passing through
reverse and rotate units) is masked out and then padded with the
selected bit pad value (RPAD and RPBIT bits in RFMT).
1h = Corresponding bit of receive data (after passing through
reverse and rotate units) is returned to CPU or DMA.
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