I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
Table 12-12. RGBLCTL Register Field Descriptions (continued)
Bit Field Type Reset Description
2 RSRCLR R/W 0h
Receive serializer clear enable bit. A write to this bit affects the
RSRCLR bit of GBLCTL.
0h = Receive serializers are cleared.
1h = Receive serializers are active.
1 RHCLKRST R/W 0h
Receive high-frequency clock divider reset enable bit. A write to this
bit affects the RHCLKRST bit of GBLCTL.
0h = Receive high-frequency clock divider is held in reset.
1h = Receive high-frequency clock divider is running.
0 RCLKRST R/W 0h
Receive clock divider reset enable bit. A write to this bit affects the
RCLKRST bit of GBLCTL.
0h = Receive clock divider is held in reset.
1h = Receive clock divider is running.
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