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SWRU543–January 2019
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-M4 Peripherals
3.3.1.17 SYSPRI1 Register (Offset = D18h) [reset = 0h]
SYSPRI1 is shown in Figure 3-17 and described in Table 3-20.
Return to Summary Table.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
NOTE: This register can only be accessed from privileged mode.
Figure 3-17. SYSPRI1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED USAGE RESERVED
R-0h R/W-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS RESERVED MEM RESERVED
R/W-0h R-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-20. SYSPRI1 Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-21 USAGE R/W 0h
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
20-16 RESERVED R 0h
15-13 BUS R/W 0h
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
12-8 RESERVED R 0h
7-5 MEM R/W 0h
Memory Management Fault Priority
This field configures the priority level of the memory management
fault. Configurable priority values are in the range 0-7, with lower
values having higher priority.
4-0 RESERVED R 0h
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